Some types of line drivers, such as 10/100BT Ethernet line drivers, comprise a segmented digital-to-analog converter (DAC) array. Each element of the segmented DAC array includes, among other components and signals, a current source transistor and operates according to a current source bias signal. To generate the output waveform from the segmented DAC, each DAC segment in the array turns on and off in various combinations at a speed of, for example, 500 MHz. Whenever DAC segments are switched off, a glitch may result on the current source input signal to that segment due to large parasitic gate-to-drain capacitance of the current source transistors. Because the current source signal is connected to all of the other DAC segments in the array, the aforementioned glitch is received at all of the segments. These glitches may result in significant overshoots and amplitude modulation beyond the applicable specification limits.